Qwen3.8-Flash-Next: faster TG on CUDA (#2373)
* Qwen3.8-Flash-Next: faster TG on CUDA * Only one thread should write to the destination
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@ -2647,9 +2647,42 @@ static void mul_mat_1row(const ggml_tensor * src0, const ggml_tensor * src1, ggm
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static __global__ void k_simple_gemm_f32(int n, int nx, const float * x, const float * y, float * z, size_t nb01, size_t nb11) {
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int ix = blockIdx.x;
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int iy = blockIdx.y;
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x += nb01 * ix;
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y += nb11 * iy;
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float sum = 0;
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for (int j = threadIdx.x; j < n; j += blockDim.x) {
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sum += x[j]*y[j];
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}
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sum = warp_reduce_sum(sum);
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__shared__ float tmp[32];
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int lane_id = threadIdx.x % WARP_SIZE;
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int warp_id = threadIdx.x / WARP_SIZE;
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if (lane_id == 0) tmp[warp_id] = sum;
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__syncthreads();
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sum = tmp[lane_id];
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sum = warp_reduce_sum(sum);
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if (threadIdx.x == 0) {
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z[iy*nx + ix] = sum;
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}
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}
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static int ggml_cuda_mul_mat(ggml_backend_cuda_context & ctx, const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst,
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const ggml_cgraph * cgraph, int node_n) {
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if (src0->type == GGML_TYPE_F32 && src1->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32 &&
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src0->ne[0] >= 1024 && src0->ne[2]*src0->ne[3] == 1 && src1->ne[2]*src1->ne[3] == 1 && src1->ne[1] <= 8) {
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auto nsm = ggml_cuda_info().devices[ctx.device].nsm;
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if (src0->ne[1] * src1->ne[1] <= nsm) {
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dim3 grid(src0->ne[1], src1->ne[1], 1);
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k_simple_gemm_f32<<<grid, 1024, 0, ctx.stream()>>>(src0->ne[0], src0->ne[1], (const float *)src0->data, (const float *)src1->data, (float *)dst->data,
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src0->nb[1]/sizeof(float), src1->nb[1]/sizeof(float));
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return node_n;
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}
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}
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// If src0 is a temporary compute buffer it may have some padding that needs to be cleared for mul_mat_vec_q or mul_mat_q.
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// But if src0 is also a view of another tensor then this cannot be done safely because it may overwrite valid tensor data.
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// Therefore, in such cases use cuBLAS.
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