Commit Graph

4846 Commits

Author SHA1 Message Date
Kawrakow c574620b12
Fix KQ mask padding for the Vulkan back-end (#2350) 2026-08-24 18:31:17 +02:00
Guy Barel 64109a4d60
vulkan : add IQ4_KS and IQ4_KT support (#2332)
* vulkan : use ggml_row_size for types with a per-row scale

Types that declare a row_meta_size store a per-row scale ahead of the row's
blocks, so a row is not ggml_type_size()*ne/ggml_blck_size() bytes. This
under-sized src0 in the four quantized mat-mul paths, and made
ggml_vk_dim01_contiguous() report such a tensor non-contiguous, which in turn
made supports_op reject it. No change for row_meta_size == 0.

* vulkan : add IQ4_KS and IQ4_KT support

A row of these types is one f32 scale followed by the row's blocks, so rows are
not a whole number of blocks apart and the usual block-indexed addressing does
not work. They are read through a uint32_t alias of binding 0 and addressed by
word; types.comp holds the alias, the stride and the decode, so each shader only
expresses its own addressing and no push constant layouts change.

Covers to_fp16, get_rows, mul_mat_vec (incl. MUL_MAT_ID) and scalar + coopmat1
mul_mm. get_rows addresses by row rather than through nb01/02/03, which cannot
express a per-row scale, so supports_op accepts only a contiguous src0 for these
two types. coopmat2 is excluded because coopMatLoadTensorNV addresses through a
uniform grid tensor layout, which cannot describe the row prefix; the two
mat-mat getters return nullptr there and the callers fall back to F16.

* tests : add IQ4_KS/IQ4_KT decode validation

Re-implements in C++ the indexing each of the four shader families uses and
diffs it against ggml's to_float over several row and block counts. CPU only: it
validates the format transcription, not the compiled shaders.
2026-08-24 18:20:35 +02:00
Samuel Oliveira Alves ad26e68bee
Apply callback to extract features in spec (#2348) 2026-08-24 12:17:23 +02:00
Thireus ☠ 477852c1c9
Load standalone Qwen3.5 MTP GGUFs passed with -md (#2328)
* Load standalone Qwen3.5 MTP GGUFs passed with -md

A predictor-only MTP GGUF reports the full block count (n_main +
nextn_predict_layers) but only ships the NextN block, so loading one
with -md failed:

  check_tensor_dims: tensor 'blk.0.attn_norm.weight' not found

create_qwen35_tensors() and create_qwen35moe_tensors() create every
main block as required. Detect the predictor-only case the same way
create_step35_tensors() does and mark the absent blocks
TENSOR_SKIP|TENSOR_NOT_REQUIRED.

Qwen3.5 also has to use the common MTP package contract, otherwise the
predictor-only GGUF is never classified as a companion, and the target
is not classified TARGET_ONLY - which is what makes it export the
hidden states the companion consumes.

The remaining two hunks cover cases the above newly reaches: a
predictor-only GGUF passed as -m now loads far enough to abort in the
graph builder, and its empty main blocks reach split_recurrent_tensors()
under -sm graph.

* Qwen3.5 MTP: require q_proj in predictor-only GGUFs, check companion arch

Review follow-up.

A dense NextN block loads q_proj as optional because it can be shared
with the last main block. A predictor-only GGUF has no main blocks, so
one built that way loaded with wq == nullptr and then hung. Require the
tensor in that case so the load fails naming it. eh_proj, attn_q and the
MLP are all optional on that block, so the tail probe stays on enorm,
which is required - the comment there said only eh_proj.

Adding Qwen3.5 to the common MTP package contract also made
common_speculative_has_recognized_mtp_companion() accept any GGUF
classified COMPANION, with no architecture check of the kind the Step
and DeepSeek branches have. Add it, plus the predictor count. Dense and
MoE are separate architectures, so the comparison is on the arch itself.
2026-08-24 10:03:27 +02:00
Samuel Oliveira Alves 66b2f50ce3
Allow dspark to draft more that the amount of block size (#2323) 2026-08-24 09:55:26 +02:00
Kawrakow 6831fa6d8e
CUDA graphs improvements (#2316)
* Give each new compute graph an unique ID

* Be more thorough with graph node comparisons
2026-08-24 09:51:59 +02:00
Kawrakow 8337e4cd38
Fix Qwen35+ MTP (#2322) 2026-08-15 19:35:03 +02:00
Kawrakow 1794846f73
Fix Gemma4 MTP (#2324)
* Fix Gemma4 MTP

* Committed this change by mistake - reverting

* Fix Gemma4 assistant crash in split mode graph

* Disable some vocabulary compatibility chacks for Gemma4 assistant drafters
2026-08-15 19:34:47 +02:00
Kawrakow 7cd62a3eb2
More principled CUDA DSA (#2315)
* DSA(CUDA): Apply softmax inverse sum at the end

* Just do V*softmax(K*Q) in f32 precision
2026-08-15 09:41:21 +02:00
Jun Yamog 8e703ddd8a
server: accept max_completion_tokens as alias for max_tokens (#2321)
OpenAI-compatible clients (e.g. pi coding agent) send
max_completion_tokens for the output token cap on custom
openai-completions providers. The server only read n_predict and
max_tokens, so the cap was silently dropped and n_predict fell back
to -1 (unlimited). This allowed runaway generations of 40k+ tokens
on long agent sessions.

Matches upstream llama.cpp behavior where max_completion_tokens is an
alias of n_predict (tools/server/server-schema.cpp).
2026-08-15 09:40:07 +02:00
Samuel Oliveira Alves 85a784505d
cast embeds for F32 if necessary (#2319) 2026-08-15 06:21:56 +02:00
Kawrakow 43afea46c2
Adapt Muse-Glimmer loading (#2314) 2026-08-14 07:55:11 +02:00
Samuel Oliveira Alves 981e5ea0d7
DSpark: gather BF16 Markov rows (#2304)
* DSpark: gather BF16 Markov rows

* DSpark: gather Markov rows by type
2026-08-13 18:02:46 +02:00
Samuel Oliveira Alves cf711918e2
Synch DFlash Tokens ID (#2303)
* llama: synchronize DFlash argmax readback

* llama: synchronize DFlash token access
2026-08-13 18:02:08 +02:00
Kawrakow 37d82c2313
Change the default amb value from 0 to 256 (#2312) 2026-08-13 17:47:37 +02:00
Kawrakow 6e7378f616
Another minor optimization on CUDA for split mode graph (#2298)
* CUDA: fuse rms -> add -> rms

* Another minor optimization on CUDA for split mode graph
2026-08-13 15:25:28 +02:00
Kawrakow 8b276c08ef
CUDA: fuse rms -> add -> rms (#2297) 2026-08-13 15:24:45 +02:00
Kawrakow 3c949f3399
Add work buffer size calculation for the ds4_comp op (#2307) 2026-08-13 15:23:38 +02:00
Kawrakow ff141691a1
Use f32 accumulation in CUDA DSA implementation (#2311) 2026-08-13 15:22:01 +02:00
Joel Farthing a10ef3eb00
laguna: compacted sliding-window KV cache (--swa-compress) (#2310)
* laguna: compacted sliding-window KV cache (--swa-compress)

* llama: fold the model-level ctx-shift gate into get_can_shift

---------

Co-authored-by: Joel Farthing <262452229+joelfarthing@users.noreply.github.com>
2026-08-13 14:54:36 +02:00
Joel Farthing 2cda8d2daf
speculative: Allow --swa-compress with DeepSeek4 MTP (#2309)
Co-authored-by: Joel Farthing <262452229+joelfarthing@users.noreply.github.com>
2026-08-13 11:45:39 +02:00
Kawrakow 4b0320381a
Fix #2183 (#2308) 2026-08-13 09:58:03 +02:00
Kawrakow ee77f7ffb8
Fix MXFP4 non-interlevaed type (#2306) 2026-08-13 08:41:39 +02:00
Marian M. 79c1e16a41
Update docs (#2299)
* Update parameters.md

- Add new parameters
- Update modified parameters
- Add graph parallel new arch
- Fix some words case

* Update README.md

- Update supported models list
- Add the new features
2026-08-13 08:05:27 +02:00
Joel Farthing 87644e36bc
model: Ling-3.0 (bailingmoe3) runtime support (#2295)
* model: Ling-3.0 (bailingmoe3) runtime support

* model: Ling-3.0-tiny support

---------

Co-authored-by: Joel Farthing <262452229+joelfarthing@users.noreply.github.com>
2026-08-13 08:02:50 +02:00
rumas77 c46ffaa566
fix dspark: seed draft block at id_last's true position (+1 off-by-one) (#2296)
The draft block was seeded at last_target_pos (the newest committed
feature row = id_last's predecessor), placing the whole block one
position early vs mainline's [id_last @ n_past, ...] convention and
colliding the seed with the newest cross-KV row. Shift the common-side
batch and the graph-side SWA mask base coherently.
2026-08-12 18:21:30 +02:00
Kawrakow 1dede1d79e
Adding Muse-Glimmer support (#2293)
* Adding Muse-Glimmer support

* Different rms_eps for post norm ops

* Need attn_post_norm split for Muse-Flimmer

* WIP: split mode graph

* Forgot this file

* Clean it up

* Minor

* Muse-glimmer: Slightly better split mode graph (+2% TG)
2026-08-12 15:53:54 +02:00
Joel Farthing 26ceed9d40
CUDA: clear MMQ row padding on partially offloaded quantized weights (#2292)
Co-authored-by: Joel Farthing <262452229+joelfarthing@users.noreply.github.com>
2026-08-11 09:07:01 +02:00
mb8565 b382ebd848
llama: pass rope freq factors to build_std_attention (#2291)
build_llama passes nullptr for the rope_factors_in argument, so
rope_freqs.weight never reaches ggml_rope_ext and llama3 rope frequency
scaling is not applied. The LLAMA_SPLIT_MODE_GRAPH branch inside
build_std_attention falls back to model.layers[il].rope_freqs, so only
the standard path is affected.
2026-08-11 08:17:25 +02:00
mb8565 c8772a8429
Fix rope type for 39 architectures (#2290)
The DFLASH case was inserted into the NEOX fall-through group in
llama_rope_type(), so the 39 cases above it now return LLAMA_ROPE_TYPE_NORM
instead of LLAMA_ROPE_TYPE_NEOX.

Move DFLASH into the NORM group so it keeps its intended rope type and the
others fall through to NEOX again.
2026-08-11 08:09:24 +02:00
Kawrakow 5763a901de
DSA: do not copy V rows when V == K (#2287) 2026-08-10 18:49:05 +02:00
Kawrakow b37189aae4
Actually fix quantized indexer cache on CUDA (#2286) 2026-08-10 18:46:02 +02:00
Kawrakow b8b3034b0f
Indexer topk: on the CPU repack Q8_0 indexer cache (#2285) 2026-08-10 18:45:43 +02:00
Samuel Oliveira Alves 7ebbb906d2
Initial implementation of DSpark (#2280)
* Implement initial arch for DSpark

* feat: Add Dspark architecture support

* avoid to many splits in graph and improve rope logic
2026-08-10 08:46:03 +02:00
abc-nix a7c81affa4
GLM-5.2 vision hack (#2283) 2026-08-09 15:54:53 +02:00
Joel Farthing 7c57e445b7
state: include compacted sliding-window rows in partial sequence state (#2281)
Co-authored-by: Joel Farthing <joel.farthing@gmail.com>
2026-08-09 11:45:05 +02:00
Kawrakow f2328aa0c1 Fix -ctk / -ctv / -ictk that I broke earlier 2026-08-08 14:41:48 +00:00
Kawrakow da5884a2db Fix not commented out fprintf 2026-08-08 14:37:35 +00:00
Kawrakow 7642ac3eca
Fix massive inefficiency in CUDA Q->f32/f16 and f32/f16->Q copies (#2279)
* CUDA indexer topk: this is better for PP

* Don't overstep

* Cleanup

* Allow Q8_0 cache in the CUDA DSA implementation

* DS4: do not cast caches to f32

* Fix massive inefficiency in CUDA Q->f32/f16 and f32/f16->Q copies

* Re-enable -ictk | --indexer-cache-type-k
2026-08-08 17:26:59 +03:00
Kawrakow daa54abd0b
DS4: do not cast caches to f32 (#2278)
* CUDA indexer topk: this is better for PP

* Don't overstep

* Cleanup

* Allow Q8_0 cache in the CUDA DSA implementation

* DS4: do not cast caches to f32
2026-08-08 17:19:23 +03:00
Kawrakow 76c1942716
Allow Q8_0 cache in the CUDA DSA implementation (#2276)
* CUDA indexer topk: this is better for PP

* Don't overstep

* Cleanup

* Allow Q8_0 cache in the CUDA DSA implementation
2026-08-08 17:18:36 +03:00
Kawrakow c5f37f0fba
Indexer topk optimization (#2274)
* CUDA indexer topk: this is better for PP

* Don't overstep

* Cleanup
2026-08-08 17:14:18 +03:00
Joel Farthing 1ce4bb9736
sweep-bench: fixes and new options (#2273)
* sweep-bench: fixes and new options

* sweep-bench: enable TG profiling markers

---------

Co-authored-by: Joel Farthing <262452229+joelfarthing@users.noreply.github.com>
2026-08-08 16:53:35 +03:00
Kawrakow 86ad770f2a
DS4: enable graph reuse (#2270)
* DS4: enable graph reuse

* Minor
2026-08-08 11:18:21 +03:00
Joel Farthing 40dffce685
CUDA: Fix non-F16 indexer top-k (#2272)
* CUDA: Fix non-F16 indexer top-k

* CUDA: Handle strided F32 indexer keys

---------

Co-authored-by: Joel Farthing <262452229+joelfarthing@users.noreply.github.com>
2026-08-07 19:35:17 +03:00
Kawrakow 61b37f5f44
Reduce the indexer temporary buffer size (#2271) 2026-08-07 17:09:18 +03:00
Kawrakow 36925b86c1 Compiler warning 2026-08-07 06:10:32 +00:00
Joel Farthing e21eed5f58
deepseek4: compacted sliding-window KV cache (--swa-compress) (#2266)
Co-authored-by: Joel Farthing <262452229+joelfarthing@users.noreply.github.com>
2026-08-07 08:36:08 +03:00
Kawrakow 466d9bb15f
Merged up/gate for DS4 (#2257)
* Merged up/gate for DS4

* Just in case

* WIP

* Fix CUDA silu kernel for merged up/gate with limit
2026-08-07 07:51:58 +03:00
Kawrakow da2293ded3
Better placement of MoE tensors with -ncmoe and 1 GPU (#2262) 2026-08-07 07:51:35 +03:00